
IDT / ICS HCSL CLOCK GENERATOR
9
ICS841602AGI REV. A JULY 10, 2008
ICS841602I
FEMTOCLOCKS CRYSTAL-TO-HCSL CLOCK GENERATOR
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC couple capacitor. A general interface diagram is
shown in
Figure 3. The XTAL_OUT pin can be left floating.
The input edge rate can be as slow as 10ns. For LVCMOS
inputs, it is recommended that the amplitude be reduced from
full swing to half swing in order to prevent signal interference
with the power rail and to reduce noise. This configuration
requires that the output impedance of the driver (Ro) plus the
series resistance (Rs) equals the transmission line impedance.
In addition, matched ter mination at the crystal input will
attenuate the signal in half. This can be done in one of two
ways. First, R1 and R2 in parallel should equal the transmission
line impedance. For most 50
Ω applications, R1 and R2 can be
100
Ω. This can also be accomplished by removing R1 and
making R2 50
Ω.
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
XTAL_IN
XTAL_OUT
VCC
R2
Ro
R1
Zo = 50
Rs
VCC
.1uf
VDD
Zo = Ro + Rs
CRYSTAL INPUT INTERFACE
The ICS841602I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in
Figure 2 below
FIGURE 2. CRYSTAL INPUt INTERFACE
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
C1
27p
X1
18pF Parallel Crystal
C2
27p
XTAL_OUT
XTAL_IN